Add DMTF mockup fixtures and test helpers

Unmodified files from DMTF Redfish-Publications (public-rackmount1, public-localstorage, public-telemetry), only those the tests use, each set with DMTF's BSD-3-Clause license and a COMMANDS.txt naming the source commit and request paths. conftest.py loads them by request path and serves a mockup over mocked HTTP, with a SessionService that hands out a token, for the transport tests.
2026-10-12 23:42:14 +00:00
1 parent 17d515d035
commit c8bcd5ace1
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+{
+    "@odata.type": "#Processor.v1_24_0.Processor",
+    "Id": "FPGA1",
+    "Name": "FPGA",
+    "ProcessorType": "FPGA",
+    "ProcessorArchitecture": "OEM",
+    "InstructionSet": "OEM",
+    "Manufacturer": "Intel(R) Corporation",
+    "Model": "Stratix 10",
+    "UUID": "00000000-0000-0000-0000-000000000000",
+    "Status": {
+        "State": "Enabled",
+        "Health": "OK"
+    },
+    "Metrics": {
+        "@odata.id": "/redfish/v1/Systems/437XR1138R2/Processors/FPGA1/ProcessorMetrics"
+    },
+    "Location": {
+        "PartLocation": {
+            "ServiceLabel": "U168",
+            "LocationType": "Embedded",
+            "LocationOrdinalValue": 0
+        }
+    },
+    "TDPWatts": 120,
+    "MaxTDPWatts": 150,
+    "ProcessorMemory": [
+        {
+            "IntegratedMemory": true,
+            "MemoryType": "HBM2",
+            "CapacityMiB": 512,
+            "SpeedMHz": 1066
+        }
+    ],
+    "FPGA": {
+        "FpgaType": "Discrete",
+        "Model": "Stratix10",
+        "FirmwareId": "0x6400002fc614bb9",
+        "FirmwareManufacturer": "Intel(R) Corporation",
+        "FirmwareVersion": "Blue v.1.00.86",
+        "HostInterface": {
+            "InterfaceType": "PCIe",
+            "PCIe": {
+                "MaxPCIeType": "Gen4",
+                "MaxLanes": 8
+            }
+        },
+        "ExternalInterfaces": [
+            {
+                "InterfaceType": "Ethernet",
+                "Ethernet": {
+                    "MaxSpeedMbps": 10240,
+                    "MaxLanes": 4
+                }
+            }
+        ],
+        "PCIeVirtualFunctions": 1,
+        "ProgrammableFromHost": true,
+        "ReconfigurationSlots": [
+            {
+                "SlotId": "AFU0",
+                "UUID": "00000000-0000-0000-0000-000000000000",
+                "ProgrammableFromHost": true,
+                "AccelerationFunction": {
+                    "@odata.id": "/redfish/v1/Systems/437XR1138R2/Processors/FPGA1/AccelerationFunctions/Compression"
+                }
+            }
+        ]
+    },
+    "AccelerationFunctions": {
+        "@odata.id": "/redfish/v1/Systems/437XR1138R2/Processors/FPGA1/AccelerationFunctions"
+    },
+    "Links": {
+        "Endpoints": [],
+        "ConnectedProcessors": [
+            {
+                "@odata.id": "/redfish/v1/Systems/437XR1138R2/Processors/CPU1"
+            }
+        ]
+    },
+    "Actions": {
+        "#Processor.Reset": {
+            "target": "/redfish/v1/Systems/437XR1138R2/Processors/FPGA1/Actions/Processor.Reset"
+        }
+    },
+    "@odata.id": "/redfish/v1/Systems/437XR1138R2/Processors/FPGA1",
+    "@Redfish.Copyright": "Copyright 2014-2026 DMTF. For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright."
+}